Equality Indicator with Tie-Offs and 7-Seg
Board bring-up circuits surround real logic with sources and indicators: power and ground rails (VCC, GND) tie off unused pins, an LED reports a condition, a probe taps an internal net for debug, and a 7-segment display shows status. The logic here asserts eq when the two 1-bit inputs match.
eq is high exactly when A equals B. The same signal lights the MATCH LED and the middle segment of the display; the remaining segments are held by VCC and GND tie-offs; a probe monitors A.
| A | B | eq | |-----|-----|------| | 0 | 0 | 1 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 |
Constraints
- Combinational logic only. The graded output is
eq. - Drive the unused display segments from constant sources: VCC (CONST1) for lit segments, GND (CONST0) for dark ones.
- Fan the equality result out to the
eqoutput, the LED, and one display segment from a single net. - Display devices (LED, PROBE, 7-seg) are visual only and are never graded.
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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