Choose your learning path

All learning tracks

26 tracks covering 1,271 problems, from a single logic gate through finite state machines, pipelining and clock domain crossing. Each track orders the catalog so one problem builds on the last.

• Digital Foundations

  Build your number system intuition. Master binary, hex, BCD, Gray code and Boolean algebra before touching a single gate.

  Logic Circuit · Easy · 60 problems

• Gate-Level Logic

  Master every fundamental gate and simplification technique. From truth tables to K-maps, learn to minimize any Boolean function.

  Logic Circuit · Easy · 68 problems

• Combinational Building Blocks

  Build adders, multiplexers, encoders and decoders from scratch. The core combinational blocks used in every digital system.

  Logic Circuit · Medium · 44 problems

• Latches and Flip-Flops

  Add memory to your circuits. Understand every latch and flip-flop type, timing constraints and type conversions.

  Logic Circuit · Medium · 129 problems

• Counters

  Design any modulus counter from ripple to synchronous. Learn lockup analysis and self-correcting counter techniques.

  Logic Circuit · Medium · 146 problems

• Shift Registers

  Master all four shift register configurations and build ring and Johnson counters. The foundation of serial communication.

  Logic Circuit · Medium · 92 problems

• Finite State Machines

  Design Moore and Mealy machines for any sequential behavior. From state diagrams to silicon-ready circuits.

  Logic Circuit · Hard · 29 problems

• Arithmetic and ALU Design

  Build the computational core of a processor. Design ALU slices, carry chains, barrel shifters and multiplier circuits.

  Logic Circuit · Hard · 34 problems

• Datapath and Storage

  Design register files, FIFOs, stacks and programmable logic arrays. The building blocks of real hardware datapaths.

  Logic Circuit · Hard · 33 problems

• Clocking and Synchronization

  Control time in your circuits. Build clock dividers, pulse generators and synchronizers that handle real-world clock domain issues.

  Logic Circuit · Medium · 89 problems

• Fault Testing and Verification

  Find and fix broken circuits. Learn stuck-at fault analysis, test vector generation and debug real circuit bugs.

  Logic Circuit · Hard · 35 problems

• Interface and Communication Circuits

  Build the FSMs and circuits that implement SPI, I2C and UART protocols from first principles.

  Logic Circuit · Hard · 80 problems

• Interview Circuit

  Hard, exam-style problems that combine every Circuit Lab skill. No hints, no skeleton circuits. Just you and the problem.

  Logic Circuit · Hard · 35 problems

• Verilog Syntax and Language Basics

  Write your first correct Verilog from day one. Master module structure, data types, operators and hierarchical instantiation.

  Verilog / SystemVerilog · Easy · 40 problems

• Combinational RTL

  Write synthesizable combinational logic in Verilog. Understand when synthesis infers a latch and how to prevent it.

  Verilog / SystemVerilog · Easy · 24 problems

• Sequential RTL

  Write clocked circuits correctly every time. Master non-blocking assignment, reset styles and flip-flop inference.

  Verilog / SystemVerilog · Medium · 31 problems

• FSM Coding

  Code any finite state machine in one, two or three always blocks. Verify Moore vs. Mealy output timing live in the waveform viewer.

  Verilog / SystemVerilog · Medium · 19 problems

• Synthesis Intuition

  Understand exactly what hardware your RTL produces. Use Yosys and NetlistViewer to verify gate structures interactively.

  Verilog / SystemVerilog · Medium · 69 problems

• Datapath Design

  Implement parameterized ALUs, barrel shifters, multipliers and arithmetic circuits used in real processors.

  Verilog / SystemVerilog · Hard · 30 problems

• Memory and Storage

  Build synchronous RAMs, register files, FIFOs and stacks in Verilog. Initialization uses case statements (no $readmemh).

  Verilog / SystemVerilog · Medium · 26 problems

• Pipelining

  Build multi-stage pipelines and handle hazards. Visualize throughput vs. latency tradeoffs live in the waveform viewer.

  Verilog / SystemVerilog · Hard · 22 problems

• Interfaces and Protocols

  Implement UART, SPI, I2C and AXI-stream handshake in RTL. Verify every byte transfer in the waveform viewer.

  Verilog / SystemVerilog · Hard · 20 problems

• SystemVerilog RTL

  Write modern synthesizable SystemVerilog. Master logic type, structs, interfaces, packed arrays and parameterized modules.

  Verilog / SystemVerilog · Medium · 29 problems

• Clock Domain Crossing and Synchronization

  Handle multi-clock designs safely. Build synchronizers, async FIFOs and reset circuits that survive real silicon.

  Verilog / SystemVerilog · Hard · 47 problems

• Debug and Verification

  Hunt bugs in broken RTL. Yosys latch detection and WaveformViewer make every bug visible and reproducible.

  Verilog / SystemVerilog · Hard · 24 problems

• Interview Circuit

  Hard RTL problems sourced from real hardware interviews at top semiconductor companies. No hints. No starter code.

  Verilog / SystemVerilog · Hard · 16 problems