Work through a topic in order, instead of picking problems at random.
26 tracks · 1,271 problems
Build your number system intuition. Master binary, hex, BCD, Gray code and Boolean algebra before touching a single gate.
Master every fundamental gate and simplification technique. From truth tables to K-maps, learn to minimize any Boolean function.
Build adders, multiplexers, encoders and decoders from scratch. The core combinational blocks used in every digital system.
Add memory to your circuits. Understand every latch and flip-flop type, timing constraints and type conversions.
Design any modulus counter from ripple to synchronous. Learn lockup analysis and self-correcting counter techniques.
Master all four shift register configurations and build ring and Johnson counters. The foundation of serial communication.
Design Moore and Mealy machines for any sequential behavior. From state diagrams to silicon-ready circuits.
Build the computational core of a processor. Design ALU slices, carry chains, barrel shifters and multiplier circuits.
Design register files, FIFOs, stacks and programmable logic arrays. The building blocks of real hardware datapaths.
Control time in your circuits. Build clock dividers, pulse generators and synchronizers that handle real-world clock domain issues.
Find and fix broken circuits. Learn stuck-at fault analysis, test vector generation and debug real circuit bugs.
Build the FSMs and circuits that implement SPI, I2C and UART protocols from first principles.
Hard, exam-style problems that combine every Circuit Lab skill. No hints, no skeleton circuits. Just you and the problem.
Write your first correct Verilog from day one. Master module structure, data types, operators and hierarchical instantiation.
Write synthesizable combinational logic in Verilog. Understand when synthesis infers a latch and how to prevent it.
Write clocked circuits correctly every time. Master non-blocking assignment, reset styles and flip-flop inference.
Code any finite state machine in one, two or three always blocks. Verify Moore vs. Mealy output timing live in the waveform viewer.
Understand exactly what hardware your RTL produces. Use Yosys and NetlistViewer to verify gate structures interactively.
Implement parameterized ALUs, barrel shifters, multipliers and arithmetic circuits used in real processors.
Build synchronous RAMs, register files, FIFOs and stacks in Verilog. Initialization uses case statements (no $readmemh).
Build multi-stage pipelines and handle hazards. Visualize throughput vs. latency tradeoffs live in the waveform viewer.
Implement UART, SPI, I2C and AXI-stream handshake in RTL. Verify every byte transfer in the waveform viewer.
Write modern synthesizable SystemVerilog. Master logic type, structs, interfaces, packed arrays and parameterized modules.
Handle multi-clock designs safely. Build synchronizers, async FIFOs and reset circuits that survive real silicon.
Hunt bugs in broken RTL. Yosys latch detection and WaveformViewer make every bug visible and reproducible.
Hard RTL problems sourced from real hardware interviews at top semiconductor companies. No hints. No starter code.