Problems

Browse the catalog

1,348 problems across gate-level logic and RTL. Every submission is compiled and simulated on the server, in Verilog, SystemVerilog or VHDL, so a passing result means the design really works.

Learning tracks

The same problems, ordered into a path you can work straight through.

• Digital FoundationsCircuit · 60
• Gate-Level LogicCircuit · 68
• Combinational Building BlocksCircuit · 44
• Latches and Flip-FlopsCircuit · 129
• CountersCircuit · 146
• Shift RegistersCircuit · 92
• Finite State MachinesCircuit · 29
• Arithmetic and ALU DesignCircuit · 34
• Datapath and StorageCircuit · 33
• Clocking and SynchronizationCircuit · 89
• Fault Testing and VerificationCircuit · 35
• Interface and Communication CircuitsCircuit · 80
• Interview CircuitCircuit · 35
• Verilog Syntax and Language BasicsVerilog · 40
• Combinational RTLVerilog · 24
• Sequential RTLVerilog · 31
• FSM CodingVerilog · 19
• Synthesis IntuitionVerilog · 69
• Datapath DesignVerilog · 30
• Memory and StorageVerilog · 26
• PipeliningVerilog · 22
• Interfaces and ProtocolsVerilog · 20
• SystemVerilog RTLVerilog · 29
• Clock Domain Crossing and SynchronizationVerilog · 47
• Debug and VerificationVerilog · 24
• Interview CircuitVerilog · 16