Debugging Read During Write Collision
A memory read controller handles outputting stored data during read operations and must guarantee read-first behavior during simultaneous read and write cycles.
Expected behavior:
| RE | WE | WD | MemData | ReadOut | |------|------|------|-----------|-----------| | 0 | 0 | 0 | 1 | 0 | | 1 | 0 | 0 | 1 | 1 | | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | | 1 | 1 | 0 | 1 | 1 |
Simulation shows ReadOut = 1 for inputs RE=1, WE=1, WD=1, MemData=0. The read output is incorrectly showing the new write data instead of the old stored data. Inspect the circuit and correct the fault.
Constraints
- The circuit must use purely combinational logic.
ReadOutmust be driven to 0 whenREis 0.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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