Debugging ROM Latch Inference
A 4-word read-only memory provides configuration constants based on a 2-bit address.
Expected behavior:
| A1 | A0 | D1 | D0 | |------|------|------|------| | 0 | 0 | 1 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 1 | | 1 | 1 | 0 | 0 |
Simulation shows D1 = 0 and D0 = 1 when the address transitions from 10 to 11. The outputs hold their previous state instead of updating to 00. Inspect the circuit and correct the fault.
Constraints
- The circuit must be purely combinational.
- No latches or flip-flops are permitted in the corrected design.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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