Full versus Empty Ambiguity
Hardware FIFOs decouple clock domains and buffer data streams between producers and consumers. A synchronous FIFO with a depth of 16 uses 4-bit pointers wr_ptr and rd_ptr. The design asserts empty when wr_ptr == rd_ptr.
The provided trace shows a sequence of 16 consecutive writes without any reads, causing wr_ptr to wrap around from 4'b1111 to 4'b0000. At this exact cycle, rd_ptr remains at 4'b0000. Analyze the pointer behavior and determine the root cause of the state ambiguity.
Constraints
- FIFO depth is exactly 16 words.
- The memory array uses 4-bit address lines.
- Both pointers are initialized to 0 on reset.
Topics
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