Moore FSM Output Delay Analysis
Replacing a Mealy machine with a Moore machine often breaks downstream modules that expect immediate data. The waveform trace provided captures the behavior of two state machines reacting to an input X. Both machines are designed to detect the sequence 101. Machine A asserts its output Y_A immediately when the final 1 is detected. Machine B asserts its output Y_B on the clock cycle following the sequence detection.
Determine the structural differences between these two implementations and identify the cause of the delay on Y_B.
Constraints
- Assume both FSMs operate on the positive edge of
clk. - Input
Xis synchronous to the clock domain. - Both machines implement an overlapping sequence detector.
Topics
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