Debugging Sequence Detector Lockup
Sequence detectors in packet routers identify frame boundaries and must recover gracefully from partial matches.
A Moore finite state machine detects the overlapping sequence 101 on input X. The machine uses four states: 0, 1, 2, and 3. Output Z is 1 only in state 3.
Expected behavior:
| Current State | X | Next State | Z | |-----------------|-----|--------------|-----| | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 2 | 0 | | 1 | 1 | 1 | 0 | | 2 | 0 | 0 | 0 | | 2 | 1 | 3 | 0 | | 3 | 0 | 2 | 1 | | 3 | 1 | 1 | 1 |
Simulation shows that after successfully detecting the sequence, supplying an input of X=0 causes the output Z to remain 1 indefinitely. The test sequence X = 1, 0, 1, 0 starting from reset produces Z = 0, 0, 1, 1 instead of the expected Z = 0, 0, 1, 0.
Inspect the circuit and correct the fault.
Constraints
- Do not add new state registers.
- The circuit must remain a Moore machine where
Zdepends only on the current state. - The
rstsignal is synchronous and active-high.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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