Mixed Assignments in State Machine
A sequence detector state machine tracks incoming data bursts and asserts a status flag when active.
Expected behavior:
The state machine has two states: 0 (Idle) and 1 (Active). The output status_flag must equal 1 whenever the next state evaluates to 1.
| rst | in_data | Next state | Next status_flag | |-------|-----------|--------------|--------------------| | 1 | X | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 1 |
Simulation shows status_flag = 0 during the first clock cycle after transitioning to state 1. The status flag output is delayed by one cycle relative to the state update. Inspect the circuit and correct the fault.
Constraints
- Do not modify the state encoding or the transition logic.
- All sequential updates must use the correct assignment operator for clocked logic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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