Data Register with Synchronous Enable
Microprocessors pause pipeline stages by holding register states across multiple clock cycles. Directly gating the clock signal introduces fatal timing glitches, so hardware designers use synchronous enables to control state updates while keeping the clock path continuous.
The circuit must capture the input data D on the rising edge of clk only when en is high. When en is low, the register must hold its current value Q on the rising clock edge.
| en | D | clk | Q (next) | |------|-----|-------|------------| | 0 | 0 | ↑ | Q | | 0 | 1 | ↑ | Q | | 1 | 0 | ↑ | 0 | | 1 | 1 | ↑ | 1 |
Constraints
- Use only standard D flip-flops and combinational logic gates.
- Do not gate or modify the
clksignal path. - Connect
clkdirectly to the clock input of the D flip-flop.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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