Register Priority Control Logic
Datapath registers frequently receive conflicting commands simultaneously. A pipeline stage might be told to hold its current value, accept an ALU result, or load data from memory all on the exact same clock cycle. The control logic must explicitly resolve these priorities to prevent undefined behavior.
Build a 4-bit register that resolves three control signals: synchronous clear (clr), parallel memory load (load), and ALU enable (en).
| clr | load | en | Next State (Q_next) | |-------|--------|------|-----------------------| | 1 | X | X | 0000 | | 0 | 1 | X | D_mem | | 0 | 0 | 1 | D_alu | | 0 | 0 | 0 | Q (Hold) |
Constraints
- Use only basic logic gates (AND, OR, NOT, XOR) and standard D flip-flops.
- Do not use pre-built multiplexer (MUX) components.
- All control logic must be strictly combinational and placed before the D flip-flops.
Topics
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