4-Bit SISO: Basic Chain Construction
Delay lines, digital filters, and serial communication interfaces rely on passing data sequentially through a chain of registers. The serial-in, serial-out (SISO) shift register acts as a digital delay line by holding a signal for a precise number of clock cycles.
Construct a 4-bit SISO shift register using D flip-flops. Data enters at D_in and propagates through the chain on the rising edge of the clock. The output Q_out must reflect the value of D_in exactly four clock cycles later. Assume all flip-flops initialize to 0.
| Clock Cycle | D_in | Q_out | Internal State (Q0, Q1, Q2, Q3) | |-------------|--------|---------|---------------------------------| | 0 (Initial) | 1 | 0 | 0, 0, 0, 0 | | 1 | 0 | 0 | 1, 0, 0, 0 | | 2 | 1 | 0 | 0, 1, 0, 0 | | 3 | 1 | 0 | 1, 0, 1, 0 | | 4 | 0 | 1 | 1, 1, 0, 1 | | 5 | 0 | 0 | 0, 1, 1, 0 |
Constraints
- Use exactly four D flip-flops.
- Connect the clock input of every flip-flop to a single shared clock signal.
- Do not use pre-packaged shift register components.
Topics
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