4-Bit SISO: Continuous Data Stream Trace
A 4-bit shift register captures the value of DIN into the first stage and shifts all stored bits one position to the right at every positive clock edge. Six signals are shown: CLK (clock, positive-edge-triggered), DIN (serial data input), and the four output stages Q0, Q1, Q2, and Q3 (all initially 0). Trace the waveforms for all four output signals Q0, Q1, Q2, and Q3 across 16 time steps to observe the continuous data pipeline.
Constraints
Q0captures the value ofDINon the LOW-to-HIGH transition ofCLK.Q1capturesQ0,Q2capturesQ1, andQ3capturesQ2simultaneously on the exact same clock edge.- Outputs hold their state when
CLKis stable or transitioning HIGH-to-LOW.
Topics
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