SR NOR Latch: Forbidden State Behavior
An SR latch typically avoids simultaneous input assertion, but in this specific logic model the forbidden state S=1 and R=1 forces both Q and Q_bar HIGH.
Four signals are shown: S (set input), R (reset input), Q (primary output, initially 0) and Q_bar (complement output, initially 1).
Trace Q and Q_bar across all 8 time steps.
Constraints
- The outputs must reflect the exact rule given for the forbidden state, temporarily violating the complement property.
- When the forbidden state ends, the outputs must resolve immediately based on the remaining asserted input.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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