3-bit Ripple Counter from Toggle Flip-Flops
The ripple counter is the simplest multi-bit counter in digital design. Each bit position is a toggle flip-flop, and the carry propagates by routing the output of one stage as the clock input of the next. It is called a ripple counter because the state changes ripple through the stages sequentially rather than all changing at once. While synchronous counters are preferred in modern designs for their predictable timing, ripple counters appear in low-power and asynchronous circuit design — and are a staple of digital design interviews as the canonical sequential circuit example.
Your task is to build a 3-bit ripple counter that counts from 0 (Q2=0, Q1=0, Q0=0) through 7 (Q2=1, Q1=1, Q0=1) and wraps back to 0. Q0 is the LSB and Q2 is the MSB. Use D flip-flops to implement T flip-flops (T=1 always, so D = NOT(Q), meaning each DFF's input is simply the complement of its own output — a single NOT gate per stage).
The three stages: Stage 0 is clocked by CLK and always toggles, producing Q0. Stage 1 is clocked by NOT(Q0) — it toggles each time Q0 transitions from 1 to 0. Stage 2 is clocked by NOT(Q1) — it toggles each time Q1 transitions from 1 to 0. The NOT gates serve dual purpose: they invert the Q output for feedback to D, and the NOT(Q0) and NOT(Q1) signals also serve as the clocks for the next stages.
Count sequence: 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000 → ...
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | CLK | input | 1 | Master clock, positive-edge triggered for stage 0 | | Q2 | output | 1 | MSB of the 3-bit count | | Q1 | output | 1 | Middle bit of the count | | Q0 | output | 1 | LSB of the count, toggles on every CLK edge |
Constraints
- Use exactly 3 DFF components and 3 NOT gates (6 components total).
- No reset input is provided — the counter initializes to an undefined state and the count sequence will become correct within 8 clock cycles.
- Stage 1's clock input is NOT(Q0), not Q0 directly — this is what creates the ripple behavior.
- Stage 2's clock input is NOT(Q1).
- This is an asynchronous counter: Q1 and Q2 do not change at the same time as Q0.
Topics
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