D Latch from a 2:1 MUX
A 2:1 multiplexer with a feedback path from its output back to one of its data inputs becomes a level-sensitive D latch — one of the most elegant structural insights in digital design. This construction shows that a MUX is not merely a selector but a universal building block capable of implementing memory. FPGA architectures exploit this: Xilinx and Intel FPGA lookup tables can be configured as latches by exploiting exactly this MUX-feedback topology.
Your task is to implement a D latch using exactly one 2:1 MUX component. The behavior: when EN=1, Q follows D (the latch is transparent). When EN=0, Q holds its previous value. The MUX implements this directly: when EN=0, the MUX selects Q (the feedback input), so Q feeds back to itself and holds. When EN=1, the MUX selects D, so Q takes on D.
The circuit: connect D to MUX input I1, connect Q (the MUX output) back to MUX input I0, and connect EN as the MUX select. When SEL=0, output = I0 = Q (hold). When SEL=1, output = I1 = D (transparent).
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | D | input | 1 | Data input: captured when EN=1 | | EN | input | 1 | Enable: when 1, Q transparently follows D; when 0, Q holds | | Q | output | 1 | Latch output |
Constraints
- Use exactly 1 MUX 2:1 component. No other gates.
- The feedback wire: Q output connects back to MUX input I0 (the input selected when EN=0).
- D connects to MUX input I1 (the input selected when EN=1).
- EN connects to the MUX select input.
Topics
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