2-bit Ring Counter
A ring counter is a circular shift register where the output of the last stage feeds back into the input of the first stage. The result is a one-hot rotating pattern: at any given time, exactly one bit in the counter is 1 and all others are 0. Ring counters appear in round-robin schedulers, rotating LED displays, and time-division multiplexing circuits because decoding the state is trivially cheap — each output directly represents which slot or resource is currently selected.
Your task is to build a 2-bit ring counter with a synchronous reset that initializes the state to 01 (Q1=0, Q0=1). After reset, the counter produces the sequence 01 → 10 → 01 → 10 → ... on successive positive clock edges. Q1 is the MSB and Q0 is the LSB.
The shift behavior: on each clock edge, Q0 shifts into Q1 (Q1_next = Q0) and Q1 shifts into Q0 (Q0_next = Q1). This creates rotation. The reset overrides this: when RST=1, Q1_next = 0 and Q0_next = 1 regardless of the current state. Implement reset using MUX components: D1 = MUX(I0=Q0, I1=0, SEL=RST) and D0 = MUX(I0=Q1, I1=1, SEL=RST).
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | CLK | input | 1 | Clock, positive-edge triggered | | RST | input | 1 | Synchronous reset: on next CLK edge, forces Q1=0 and Q0=1 | | Q1 | output | 1 | MSB of the ring counter | | Q0 | output | 1 | LSB of the ring counter; initialized to 1 after reset |
Constraints
- Use exactly 2 DFF and 2 MUX components (4 total). No other gates needed.
- RST is synchronous: the counter loads 01 on the first positive clock edge after RST=1, not immediately.
- The rotation pattern after reset is strictly 01 → 10 → 01 → 10, never 00 or 11.
- Connect MUX I1 input to constant 0 for Q1's reset path and constant 1 for Q0's reset path.
Topics
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