Reconvergence of Individually Synchronized Bits
A 32-bit address bus transfers memory access requests from a 100 MHz processor domain to a 125 MHz peripheral domain.
Expected behavior: The destination domain must receive the exact 32-bit value transmitted on Addr_In accompanied by a synchronized Valid_Out pulse. Data corruption must not occur during transitions.
Simulation shows transient invalid addresses appearing on Addr_Out during domain crossing. When Addr_In transitions from 65535 to 65536, the destination domain asserts Valid_Out while sampling 131071. Inspect the circuit and correct the fault.
Constraints
- Multi-bit data buses must not use parallel 2-flop synchronizers.
- A handshake protocol or asynchronous FIFO must be used to transfer the data bus.
- The synchronized data must only be read when the corresponding valid signal is asserted.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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