Handshake Deadlock Due to Early Reset
A valid-acknowledge handshake protocol transfers data reliably across asynchronous clock boundaries. The source controller asserts req_out when req_in is high and waits for ack_in to go high before returning to idle. If the destination domain resets during a transaction, the source controller must abort the transaction to prevent a deadlock.
Expected behavior:
| Current State | req_in | ack_in | rst_dst | Next State | req_out | |---------------|----------|----------|-----------|------------|-----------| | IDLE | 0 | X | X | IDLE | 0 | | IDLE | 1 | X | X | WAIT_ACK | 1 | | WAIT_ACK | X | 0 | 0 | WAIT_ACK | 1 | | WAIT_ACK | X | 1 | 0 | IDLE | 0 | | WAIT_ACK | X | X | 1 | IDLE | 0 |
Simulation shows req_out = 1 indefinitely when rst_dst = 1 is applied during an active request with ack_in = 0. The source domain is stuck in the WAIT_ACK state.
Inspect the circuit and correct the fault.
Constraints
- Do not alter the normal handshake transition logic.
- The FSM must return to the IDLE state immediately on the next clock edge when
rst_dstis asserted. - Assume all inputs are properly synchronized to the source clock domain.
Topics
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