Partial Pipeline Reset
Pipelined data paths often leave data buses unreset to save routing resources, relying on control signals to invalidate garbage data. A 1-stage pipeline register captures d_in and valid_in on the rising edge of the clock, utilizing a synchronous rst signal to initialize the pipeline state.
Expected behavior:
| rst | valid_in | d_in | valid_out (next cycle) | d_out (next cycle) | |-------|------------|--------|--------------------------|----------------------| | 1 | X | X | 0 | 0 | | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 1 | 1 | | 0 | 0 | 1 | 0 | 1 |
Simulation shows valid_out = 1 on the cycle immediately following a reset when valid_in = 1. The downstream consumer is processing garbage data on startup because the pipeline control state fails to initialize correctly. Inspect the circuit and correct the fault.
Constraints
- Do not add additional flip-flops to the circuit.
- The reset behavior must be strictly synchronous.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.