Critical Path Identification
A digital pipeline can only run as fast as its slowest combinational stage. Identifying the bottleneck is the first step in timing optimization for high-performance hardware.
The system described below represents a three-stage pipeline processing 16-bit data. Stage 1 computes A + B using a ripple-carry adder. Stage 2 multiplies the result by a constant using a shift-and-add network. Stage 3 performs a bitwise XOR with a mask M.
All registers have a setup time of 2ns and a clock-to-q delay of 1ns. The ripple-carry adder has a combinational delay of 32ns. The multiplier network has a delay of 45ns. The XOR gate has a delay of 1ns.
Determine the critical path and calculate the timing limits of this pipeline.
Constraints
- All registers are edge-triggered D flip-flops.
- Clock skew and jitter are assumed to be zero.
- Wire delay is considered negligible.
Topics
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