Identifying False Critical Paths
Static timing analysis tools often report timing violations on combinational paths that can never logically occur during actual operation. The circuit below shows a pipelined datapath with two execution units fed by a common source register R1 and feeding a destination register R2. A multiplexer selects between a fast path through ALU1 with a logic delay of 2ns, and a slow path through ALU2 with a logic delay of 8ns. The control signal mode_select drives both the execution units and the multiplexer selection logic. Due to an inverted control wire, when mode_select enables ALU2, the multiplexer is forced to route a zero-constant path (0ns delay) instead of the ALU2 output. Analyze the timing arcs and logical dependencies. Determine the true critical path delay and identify which reported paths are false.
Constraints
- Assume setup time (
tsu) and clock-to-q (tcq) of all registers are 0ns for this analysis. - The multiplexer has a propagation delay of 1ns.
- Routing delays between components are negligible (0ns).
Topics
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