Flush vs Stall Waveform Analysis
Modern superscalar processors rely on precise pipeline control to handle hazards without dropping valid instructions.
The provided waveform captures a three-stage pipeline processing sequential instructions. The signals include clk, valid_in, stall, flush, and internal pipeline stage registers stage1_data, stage2_data, and stage3_data. A gap appears in the valid_out signal during cycles 5 through 7.
Analyze the register transitions during the gap. Determine whether the pipeline control logic issued a stall or a flush, and identify the cycle where the control action was triggered.
Constraints
- Assume a synchronous active-high reset.
- All pipeline registers update on the rising edge of
clk.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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