Clock Gate Enable Crossing Domains
A power management controller generates an enable signal pm_en in a slow clock domain to gate a high-speed core clock clk_fast.
Expected behavior:
The gated clock clk_gated must cleanly pass clk_fast pulses when the power management enable is active. The enable signal must safely cross into the high-speed domain to avoid setup and hold violations at the clock gating cell.
Simulation shows that clk_gated exhibits a glitch when pm_en transitions from 1 to 0. Timing analysis reports a setup time violation at the latch inside the integrated clock gating cell. Inspect the circuit and correct the fault.
Constraints
- Do not modify the internal structure of the integrated clock gating (ICG) cell itself.
- Use standard D-type flip-flops to build the required synchronization logic.
- The synchronized enable signal must drive the existing clock gating cell.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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