FIFO Empty Logic Evaluated in Wrong Domain
An asynchronous FIFO safely transfers data between two independent clock domains. The full flag prevents overflow in the write domain, while the empty flag prevents underflow in the read domain.
Expected behavior:
The empty flag must assert immediately when the read pointer r_ptr catches up to the synchronized write pointer w_ptr_sync in the read clock domain.
Simulation shows the empty flag asserting late during a burst read operation. When r_en is high and the FIFO contains one remaining word, a subsequent read operation executes before the empty flag updates. This causes an underflow. Test waveforms indicate the empty flag is delayed by several clock cycles relative to the pointers updating.
Inspect the circuit and correct the fault.
Constraints
- Do not modify the
fullflag generation logic. - The
emptyflag must evaluate combinationally in the read clock domain. - Use the synchronized write pointer
w_ptr_syncfor the empty condition evaluation.
Topics
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