Debug: Asynchronous Clear Glitch
A modulo-5 counter tracks sequences from 0 to 4 and wraps back to 0 on the next clock edge.
Expected behavior:
When the active-high Reset is 0, the counter increments its outputs Q2, Q1, and Q0 on each rising edge of Clk. When the state reaches Q2=1, Q1=0, Q0=0 (decimal 4), the next rising clock edge must transition the state to Q2=0, Q1=0, Q0=0.
Simulation shows that the counter increments correctly up to state 3. On the next rising edge, it transitions to state 4 but immediately drops to state 0 before the next clock cycle begins. The test case for holding state 4 fails because Q2, Q1, and Q0 evaluate to 0, 0, and 0 prematurely. Inspect the circuit and correct the fault.
Constraints
- Do not add any new flip-flops to the circuit
- The reset mechanism must be purely synchronous
- All state transitions must occur only on the rising edge of
Clk
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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