4-Bit SISO with Shift Enable
Buffered pipelines and serial communication interfaces must pause transmission when the receiver is not ready. A shift enable signal allows the shift register to freeze its state without interrupting the continuous global clock.
The circuit is a 4-bit Serial-In Serial-Out (SISO) shift register with an active-high enable signal EN. When EN is 1, data at sin shifts into the first stage on the rising edge of clk, and each subsequent stage receives the value of the previous stage. When EN is 0, all stages retain their current values. The output sout reflects the final stage.
| EN | clk | Q0 | Q1 | Q2 | sout | |------|-------|------|------|------|--------| | 0 | Rising | Q0 | Q1 | Q2 | sout | | 1 | Rising | sin| Q0 | Q1 | Q2 |
Constraints
- Do not connect the
ENsignal to the clock pin of any flip-flop. - Connect the global clock directly to the clock pin of every flip-flop.
- Use a 2:1 multiplexer at the
Dinput of each flip-flop to select between the hold state and the shift state. - Implement exactly 4 stages of shifting using D flip-flops.
Topics
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