SISO as a Programmable Delay Line: Tap Selection
Variable-delay lines synchronize data in pipeline alignment, digital echo circuits, and high-speed test equipment. By tapping different stages of a shift register chain, a single circuit can dynamically adjust signal latency without altering the system clock.
Construct a 4-stage Serial-In Serial-Out (SISO) shift register with a selectable output tap. The circuit receives a serial input D and propagates it through four sequential register stages (Q0 through Q3) on each rising edge of CLK. A 2-bit select signal SEL determines which stage drives the final output Y, providing a programmable delay of 1 to 4 clock cycles.
| SEL | Y | Effective Delay | |-------|-----|-----------------| | 0 | Q0| 1 cycle | | 1 | Q1| 2 cycles | | 2 | Q2| 3 cycles | | 3 | Q3| 4 cycles |
Constraints
- Use exactly four D flip-flops to form the shift register.
- Implement the tap selection using combinational logic or a multiplexer.
- The shift register must advance state strictly on the rising edge of
CLK. - Do not use pre-built shift register macros or delay blocks.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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