SISO: Clock Missing on One Stage Debug
A 4-bit Serial-In Serial-Out (SISO) shift register delays an incoming data stream by exactly four clock cycles. The circuit cascades four D flip-flops, shifting the value of D sequentially through internal stages Q0, Q1, Q2, and finally to the output Q3 on each rising edge of CLK.
Expected behavior:
When a sequence of bits is applied to D, the output Q3 must reproduce that exact sequence four clock cycles later. All internal states initialize to 0 when RST is asserted high.
Simulation shows that after applying D = 1 for five consecutive clock cycles, the output Q3 remains 0. Internal probing reveals that the first two stages capture data correctly, but the third and fourth stages never change state regardless of the input.
Inspect the circuit and correct the fault.
Constraints
- Do not add or remove any flip-flops.
- Only modify the existing wiring to correct the signal flow.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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