SISO: Wrong D-to-Q Wiring Debug
A 4-bit Serial-In Serial-Out (SISO) shift register delays an incoming data stream by four clock cycles.
Expected behavior:
Data applied at D_in propagates through four sequential flip-flop stages and appears at Q_out exactly four clock cycles later.
| Clock Edge | D_in (before edge) | Q_out (after edge) | |------------|----------------------|----------------------| | 1 | 1 | 0 | | 2 | 0 | 0 | | 3 | 0 | 0 | | 4 | 0 | 1 | | 5 | 0 | 0 |
Simulation shows that a logic 1 entered at D_in exits at Q_out after 3 cycles instead of 4. The overall latency of the shift register is incorrect. Inspect the circuit and correct the fault.
Constraints
- Do not add or remove any flip-flops.
- Only modify the incorrect wire connection.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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