4-Bit SISO: Pipeline Latency Waveform
A 4-bit serial-in serial-out shift register delays the input signal by four clock cycles, shifting data one stage to the right on each positive clock edge.
Six signals are shown: CLK (clock, period 2), D (serial input), and the four register stages Q0, Q1, Q2, and Q3 (outputs, all initially 0).
Trace all four output signals Q0, Q1, Q2, and Q3 across all 12 time steps.
Constraints
- All output stages are initially 0 at time step 0.
- Data shifts strictly on the LOW-to-HIGH transition of
CLK. - A value present at
Dright before the rising edge determines the new state ofQ0.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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