SISO with Synchronous Clear
Data pipelines and communication interfaces require a mechanism to flush stale bits before loading a new data frame. A 4-bit serial-in, serial-out shift register with synchronous clear provides this capability by resetting all internal stages precisely on the clock edge.
The circuit shifts data from din to dout across four clock cycles. When clr is asserted high, the next rising edge of the clock must force all internal flip-flop states to 0 simultaneously. The output dout represents the state of the final flip-flop in the chain.
To maintain synchronous operation, the clear signal must be integrated into the data path of each stage. For any given stage, the effective data input (D_next) depends on the previous stage's output (Q_prev) and the clr signal:
| clr | Q_prev | D_next | |-------|----------|----------| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 0 | | 1 | 1 | 0 |
*(Note: For the first stage, Q_prev is din.)*
Constraints
- Use exactly four D flip-flops.
- Implement the synchronous clear using combinational logic on the D inputs.
- Do not use asynchronous reset pins on the flip-flops.
Topics
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