Two 4-Bit SISOs in Series: Total Latency
Two positive-edge-triggered 4-bit Serial-In Serial-Out (SISO) shift registers are cascaded in series to form an 8-bit pipeline. Four signals are shown: CLK (clock, period 2), DIN (input to the first stage), Q1_OUT (output of the first stage, initially 0), and Q2_OUT (output of the second stage, initially 0). Trace the intermediate signal Q1_OUT and the final output Q2_OUT across all 20 time steps.
Constraints
- Both shift registers are positive-edge-triggered and update their state only on the LOW-to-HIGH transition of the clock.
- The output of the first shift register (
Q1_OUT) connects directly to the input of the second shift register. - The shift registers initially hold all zeros.
Topics
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