FSM Logic Optimized Away
A UART transmitter uses a finite state machine to serialize data and drive the external transmit pin. The combinational logic block computes the next state bits N1 and N0 and the output TX based on current state bits S1 and S0 and the Data bit.
Expected behavior:
| S1 | S0 | Data | TX | N1 | N0 | |------|------|--------|------|------|------| | 0 | 0 | 0 | 1 | 0 | 1 | | 0 | 0 | 1 | 1 | 0 | 1 | | 0 | 1 | 0 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | 0 | | 1 | 0 | 0 | 0 | 1 | 1 | | 1 | 0 | 1 | 1 | 1 | 1 | | 1 | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 |
Simulation shows TX = 0 for input S1=0, S0=0, Data=0. The transmit pin incorrectly remains 0 during the IDLE state. Inspect the circuit and correct the fault.
Constraints
- Do not modify the next-state logic paths for
N1andN0. - Ensure the
TXoutput is properly driven by the state and data inputs.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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