Debug Sequential: Output Logic Glitch in Mealy Machine
Mealy machine outputs evaluate immediately based on current state and inputs, making downstream circuits vulnerable to false triggers if the combinational logic is flawed.
Expected behavior:
| X | S1 | S0 | Y | |-----|------|------|-----| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 |
Hardware testing shows an unintended output pulse causing false triggers on a downstream asynchronous reset. Simulation isolates the issue: Y = 1 for inputs X=0, S1=1, S0=0. The output logic asserts high incorrectly during this state. Inspect the circuit and correct the fault.
Constraints
- Do not modify the state registers or input wiring.
- Only replace the faulty logic gate in the output path.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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