Debug Sequential: Missing State Machine Reset
A control state machine manages operational phases and must initialize to a known idle state upon power up.
Expected behavior:
| rst | en | Current Q1 Q0 | Next Q1 Q0 | |-------|------|-----------------|--------------| | 1 | 0 | X X | 0 0 | | 1 | 1 | X X | 0 0 | | 0 | 0 | Q1 Q0 | Q1 Q0 | | 0 | 1 | 0 0 | 0 1 | | 0 | 1 | 0 1 | 1 0 | | 0 | 1 | 1 0 | 1 1 | | 0 | 1 | 1 1 | 0 0 |
Simulation shows the initialization test fails. When rst = 1 is applied at startup, the state outputs do not transition to Q1 = 0 and Q0 = 0. The state machine powers up in an invalid state and deadlocks. Inspect the circuit and correct the fault.
Constraints
- Do not modify the combinational next-state logic.
- Do not add new flip-flops or remove existing ones.
- Only add or modify routing for the reset network.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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