1-to-4 Demultiplexer from AND and NOT Gates
A demultiplexer routes a single data input to one of several outputs based on a select signal. It is the inverse of a multiplexer: where a mux selects one of many inputs, a demux distributes one input to one of many outputs. Demuxes appear in bus fanout circuits, memory address decoding, and data routing in network switch fabrics. Understanding how to build one from primitive gates demonstrates the AND-enable structure that underlies all address decoders.
Your task is to build a 1-to-4 demultiplexer. The circuit has one data input (D), two select bits (S1 as MSB, S0 as LSB), and four outputs (Y0, Y1, Y2, Y3). Each output is either equal to D (if that output is selected) or 0 (if not selected). Only one output can equal D at any time.
Selection encoding: S1=0, S0=0 → Y0 = D, Y1=Y2=Y3=0 S1=0, S0=1 → Y1 = D, Y0=Y2=Y3=0 S1=1, S0=0 → Y2 = D, Y0=Y1=Y3=0 S1=1, S0=1 → Y3 = D, Y0=Y1=Y2=0
Each output is the AND of D with the appropriate combination of S1, S0 and their complements: Y0 = D AND NOT(S1) AND NOT(S0), Y1 = D AND NOT(S1) AND S0, Y2 = D AND S1 AND NOT(S0), Y3 = D AND S1 AND S0.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | D | input | 1 | Data input, routed to the selected output | | S1 | input | 1 | Select MSB | | S0 | input | 1 | Select LSB | | Y0 | output | 1 | Output 0: equals D when S1=0, S0=0; else 0 | | Y1 | output | 1 | Output 1: equals D when S1=0, S0=1; else 0 | | Y2 | output | 1 | Output 2: equals D when S1=1, S0=0; else 0 | | Y3 | output | 1 | Output 3: equals D when S1=1, S0=1; else 0 |
Constraints
- Only AND and NOT gates are allowed. No OR, XOR, NAND, NOR, or MUX.
- The optimal solution uses 2 NOT gates (for NOT_S1 and NOT_S0) and 4 AND3 gates (one per output), totaling 6 components.
- Exactly one output is non-zero at any time. When D=0, all outputs are 0 regardless of the select.
- The circuit is purely combinational. No clock or state.
Topics
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