Extract Expression from a Two-Level AND-OR Circuit with Fan-Out
Physical routing channels in silicon often distribute a single input signal to multiple logic gates to reduce pad count and area.
The schematic presents a two-level AND-OR circuit with three inputs A, B, and C, and one output Y. Input B splits at a fan-out node, feeding into both a top AND gate and a bottom AND gate. The top AND gate receives inputs A and B. The bottom AND gate receives inputs B and C. The outputs of both AND gates feed into a final OR gate.
Determine the Boolean expression at Y and evaluate the circuit behavior under specific input conditions.
Constraints
- Assume ideal logic gates with zero propagation delay.
- Fan-out nodes distribute the exact same logical value to all connected gate inputs.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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