UART Receiver State Machine
Every serial communication interface requires a controller to frame incoming bits into parallel words. The UART receiver state machine is the core control logic that guides data reception through the standard serial protocol phases.
The circuit must transition exactly through Idle (00), Start (01), Data (10), and Stop (11) states. The 2-bit output state represents the current state of the machine. State transitions occur on the rising edge of clk. When the synchronous rst is 1, the state resets to 00. When rst is 0, the next state is determined by the 1-bit baud_tick, the 1-bit serial line rx, and the 3-bit bit_count according to the following logic:
| state | baud_tick | rx | bit_count | Next state | |---------|-------------|------|-------------|--------------| | 00 | 0 | X | XXX | 00 | | 00 | 1 | 1 | XXX | 00 | | 00 | 1 | 0 | XXX | 01 | | 01 | 0 | X | XXX | 01 | | 01 | 1 | X | XXX | 10 | | 10 | 0 | X | XXX | 10 | | 10 | 1 | X | != 111 | 10 | | 10 | 1 | X | 111 | 11 | | 11 | 0 | X | XXX | 11 | | 11 | 1 | X | XXX | 00 |
Constraints
- Use only D flip-flops for state storage.
- Implement synchronous reset logic.
- State encoding must match the provided table exactly.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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