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Codiode/Problems/FSM Design

Incomplete Default State Assignment

MediumLogic CircuitDebug

A finite state machine next-state logic block determines the transition path based on the current state and input signals.

Expected behavior:

| S1 | S0 | go | N1 | N0 | |------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 |

Synthesis tools flag an inferred latch in this combinational block. Simulation shows N1 = 0 and N0 = 0 for input S1=0, S0=1, go=1. The next-state logic fails to output the expected 01 to maintain the current state, dropping to 00 instead. Inspect the circuit and correct the fault.

Constraints

  • The circuit must remain purely combinational with no flip-flops or feedback loops.
  • Do not modify the input or output port definitions.

Topics

fsmcombinational-logicsynthesisdebug

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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