Missing State Transition
A UART receiver finite state machine (FSM) controls the sampling of incoming serial data. The FSM must transition from the STOP state (11) back to the IDLE state (00) upon detecting a valid stop bit (RX = 1) to prepare for the next byte.
Expected behavior:
| S1 | S0 | RX | N1 | N0 | |------|------|------|------|------| | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | 1 | | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 0 | 0 |
Simulation shows that after successfully receiving the first byte, the FSM remains in the STOP state indefinitely. For input S1=1, S0=1, RX=1, the output evaluates to N1=1, N0=1 instead of 0, 0. The receiver freezes and drops all subsequent bytes.
Inspect the circuit and correct the fault.
Constraints
- Do not add new states to the FSM logic.
- Modify only the broken transition logic for the
STOPstate.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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