2-to-4 Line Decoder with Active-High Enable
A line decoder is one of the most fundamental building blocks in digital systems. You find it inside every memory chip, every address bus interface, and every peripheral select circuit. Its job is straightforward: given an N-bit binary address, assert exactly one of 2^N output lines. The enable input makes the decoder controllable: when EN is low the decoder is silenced completely and none of its outputs can fire.
Your circuit has a 2-bit address bus made up of signals A1 (the most-significant bit) and A0 (the least-significant bit). Together they encode one of four possible selections: line 0 through line 3. A separate active-high enable signal EN acts as the master gate. When EN is 0 every output is forced to 0, regardless of the address. When EN is 1 the circuit decodes normally: exactly one output goes high based on the address, and the remaining three stay low at all times.
The complete truth table covering all eight input combinations is shown below. Each enabled row produces a one-hot output pattern: exactly one Y is high and three are low. Every disabled row produces an all-zero output.
| EN | A1 | A0 | Y3 | Y2 | Y1 | Y0 | |----|----|----|----|----|----|-----| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
Each output can be described by a single Boolean product term: Yi is true when EN is asserted and the address bits match the binary encoding of i. For example Y2 is high when EN AND A1 AND NOT(A0) are all true simultaneously. Designing each output as its own product term and sharing any inverted signals across outputs is the direct path to the minimum component count.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | EN | input | 1 | Active-high enable. When 0 all outputs are forced low | | A1 | input | 1 | Address most-significant bit | | A0 | input | 1 | Address least-significant bit | | Y0 | output | 1 | Asserted when EN=1, A1=0, A0=0 | | Y1 | output | 1 | Asserted when EN=1, A1=0, A0=1 | | Y2 | output | 1 | Asserted when EN=1, A1=1, A0=0 | | Y3 | output | 1 | Asserted when EN=1, A1=1, A0=1 |
Constraints
- Purely combinational circuit. No flip-flops, latches, or clock inputs
- At most one output may be high at any time; two or more outputs high simultaneously is always incorrect
- When EN=0 all four outputs must be exactly 0, regardless of A1 and A0
- The NOT of A1 and the NOT of A0 each appear in two output expressions. Share those inverted signals rather than duplicating NOT gates
- AND3 (3-input AND) is available and counts as a single component; using it directly for each product term leads to the minimum gate count
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