Odd Parity Bit Generator for 3-bit Data
Every UART frame appends a single parity bit so the receiver can catch single-bit transmission errors. This is that circuit.
Given three data bits D2, D1, D0, produce an output P such that the total count of 1s across all four signals {D2, D1, D0, P} is always odd. When the data already contains an odd number of 1s, P must be 0. When the data contains an even number of 1s (including zero), P must be 1.
| D2 | D1 | D0 | 1s in data | P | |----|----|----|------------|---| | 0 | 0 | 0 | 0 (even) | 1 | | 0 | 0 | 1 | 1 (odd) | 0 | | 0 | 1 | 0 | 1 (odd) | 0 | | 0 | 1 | 1 | 2 (even) | 1 | | 1 | 0 | 0 | 1 (odd) | 0 | | 1 | 0 | 1 | 2 (even) | 1 | | 1 | 1 | 0 | 2 (even) | 1 | | 1 | 1 | 1 | 3 (odd) | 0 |
Example: D2=1, D1=1, D0=0 → three signals contain two 1s (even), so P=1, giving a total of three 1s across all four signals (odd). ✓
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | D2 | input | 1 | Data bit 2 (most significant) | | D1 | input | 1 | Data bit 1 | | D0 | input | 1 | Data bit 0 (least significant) | | P | output | 1 | Parity bit set to make total 1-count odd |
Constraints
- Purely combinational. No clock, no flip-flops
- Optimal solution uses 3 components total
- No restriction on gate types
Topics
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