IEEE 754 Leading Zero Counter
Floating point arithmetic units require normalization of the mantissa after addition or subtraction. Determining the exact left-shift amount to restore the hidden bit is the critical path in a modern FPU.
The circuit takes a 4-bit input A and calculates the number of leading zeros starting from the most significant bit. It outputs a 2-bit count representing the shift amount. It also outputs a 1-bit valid signal that asserts high when the input contains at least one high bit, indicating the count is meaningful. When A is entirely zero, valid must be 0 and count must be 0.
| A | valid | count | |-----|---------|---------| | 0000 | 0 | 00 | | 0001 | 1 | 11 | | 0010 | 1 | 10 | | 0011 | 1 | 10 | | 0100 | 1 | 01 | | 0101 | 1 | 01 | | 0110 | 1 | 01 | | 0111 | 1 | 01 | | 1000 | 1 | 00 | | 1001 | 1 | 00 | | 1010 | 1 | 00 | | 1011 | 1 | 00 | | 1100 | 1 | 00 | | 1101 | 1 | 00 | | 1110 | 1 | 00 | | 1111 | 1 | 00 |
Constraints
- Use only combinational logic gates.
- Do not use any sequential elements or clocks.
Topics
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