BCD Adder Correction Block
Arithmetic pipelines processing human-readable data rely on Binary-Coded Decimal representations. Standard binary adders produce invalid hex characters when a digit sum exceeds nine, requiring a dedicated correction stage to restore base-10 validity.
The circuit receives a 4-bit input sum S and a 1-bit flag. When flag is 1, the circuit adds 6 (binary 0110) to S. When flag is 0, S passes through unmodified. The circuit outputs the corrected 4-bit sum Y and any resulting carry out Cout.
| flag | S | Y | Cout | |--------|-----|-----|--------| | 0 | 5 | 5 | 0 | | 0 | 9 | 9 | 0 | | 1 | 0 | 6 | 0 | | 1 | 10 | 0 | 1 | | 1 | 15 | 5 | 1 |
Constraints
- Combinational logic only.
- Implement using standard logic gates and adders.
Topics
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