Two's Complement Inverter
ALUs and DSP pipelines frequently need to negate signed integer values on the fly. The standard method for negating a binary number in hardware is taking its two's complement.
The circuit receives a 4-bit input A and must produce a 4-bit output Y representing the negative value of A. The two's complement operation consists of a bitwise inversion followed by an addition of one.
| A[3:0] | Y[3:0] | |----------|----------| | 0000 | 0000 | | 0001 | 1111 | | 0111 | 1001 | | 1000 | 1000 |
Constraints
- Use exactly one 4-bit adder.
- Do not instantiate a second adder or incrementer block.
- Drive the carry-in port of the adder to perform the plus-one operation.
Topics
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