Multiplier Partial Product Generator
High-performance hardware multipliers rely on massive arrays of parallel AND gates before applying Wallace or Dadda reduction trees. The partial product generator is the foundational first stage that creates this grid of bitwise products.
Generate all 16 partial products for two 4-bit inputs A and B. Route these products into seven output buses W0 through W6 corresponding to their binary weight. The binary weight of a product A[i] AND B[j] is i + j.
For each output bus, assign the products starting with the lowest index of A to the lowest index of the bus:
| Bus | Width | Product Mapping (LSB to MSB) | |-----|-------|------------------------------| | W0 | 1-bit | A[0]&B[0] | | W1 | 2-bit | A[0]&B[1], A[1]&B[0] | | W2 | 3-bit | A[0]&B[2], A[1]&B[1], A[2]&B[0] | | W3 | 4-bit | A[0]&B[3], A[1]&B[2], A[2]&B[1], A[3]&B[0] | | W4 | 3-bit | A[1]&B[3], A[2]&B[2], A[3]&B[1] | | W5 | 2-bit | A[2]&B[3], A[3]&B[2] | | W6 | 1-bit | A[3]&B[3] |
Constraints
- Use exactly 16 AND gates.
- Combinational logic only.
- No adders or higher-level multiplier blocks.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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