Underscores for Readability

Long binary constants in RTL code are notoriously difficult to read and prone to transcription errors during code review. Verilog allows the use of underscores to group digits, typically separating them into 4-bit nibbles, which vastly improves readability without affecting the synthesized hardware.

This module applies a fixed 32-bit bitmask to an incoming 32-bit data word. The internal fixed pattern is 10101011110011011110111100000001. The module performs a bitwise AND between the data_in port and this fixed pattern, assigning the result to the data_out port. To practice good coding standards, the fixed pattern must be written in the RTL as a 32-bit binary literal with an underscore separating every 4-bit nibble.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | data_in | input | 32 | Incoming data word | | data_out | output | 32 | Result of bitwise AND between data_in and the fixed pattern |

Constraints

• The module must be purely combinational.
• The assigned fixed pattern must exactly match the 32-bit sequence specified.
• The fixed pattern must be written using binary format with underscores every four bits.

Topics

Related problems

• Single Continuous AssignmentEasy
• Basic Vector ConcatenationEasy
• Ternary Operator MuxEasy
• Left Hand Side ConcatenationEasy
• Explicit Binary LiteralsEasy
• Inout Port MechanicsEasy
• Vector Port EndiannessEasy
• Basic Module PortsEasy