Basic Vector Concatenation
Microprocessors and peripheral controllers frequently generate separate 1-bit status flags to indicate conditions like overflow, parity error, or completion. To read these flags efficiently over a system bus, they must be packed into a single multi-bit word.
Combine four individual 1-bit input flags into a single 4-bit output vector. The output status_bus must map flag_a to bit 3 (the most significant bit), flag_b to bit 2, flag_c to bit 1, and flag_d to bit 0 (the least significant bit).
This is a purely combinational circuit. The output must reflect the current inputs immediately without any clock or reset synchronization.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | flag_a | input | 1 | Flag mapped to MSB (bit 3) | | flag_b | input | 1 | Flag mapped to bit 2 | | flag_c | input | 1 | Flag mapped to bit 1 | | flag_d | input | 1 | Flag mapped to LSB (bit 0) | | status_bus | output | 4 | Concatenated status word |
Constraints
- The output
status_busmust be driven combinationally. - The bit ordering must exactly match the specification with
flag_amapped to the MSB. - Do not use sequential logic.
Topics
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