The Incomplete Case Latch
Hardware synthesis tools map RTL code into physical gates. When a combinational logic block specifies outputs for some, but not all, possible input conditions, the synthesizer assumes the circuit must remember its previous state. It infers a latch to hold the previous value. This creates unintended sequential logic, leading to timing violations, glitch sensitivity, and larger area.
A custom instruction decoder maps a 4-bit binary-coded decimal input into an 8-bit control signal. The input has 16 possible binary states, but only the values 0 through 9 are valid instructions. The hardware must explicitly drive the output to zero for the 6 invalid states to guarantee that a purely combinational circuit is synthesized.
The module computes the following mapping: • sel = 0 outputs 8'h01 • sel = 1 outputs 8'h02 • sel = 2 outputs 8'h04 • sel = 3 outputs 8'h08 • sel = 4 outputs 8'h10 • sel = 5 outputs 8'h20 • sel = 6 outputs 8'h40 • sel = 7 outputs 8'h80 • sel = 8 outputs 8'hAA • sel = 9 outputs 8'h55 • All other values of sel (10 through 15) output 8'h00
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | sel | input | 4 | Selection input representing a decimal value from 0 to 15 | | out | output | 8 | Decoded control signal; invalid inputs must output zero |
Constraints
- The circuit must be purely combinational.
- No clock or reset signals are present.
- The output must be exactly
8'h00for inputs 10, 11, 12, 13, 14, and 15.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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